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November 1998 PRELIMINARY
ML4827* Fault-Protected PFC and PWM Controller Combo
GENERAL DESCRIPTION
The ML4827 is a controller for power factor corrected, switched mode power supplies, that includes circuitry necessary for conformance to the safety requirements of UL1950. A direct descendent of the industry-standard ML4824-1, the ML4827 adds a TriFault DetectTM function to guarantee that no unsafe conditions may result from single component failure in the PFC. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. The ML4827 includes circuits for the implementation of a leading edge, average current, "boost" type power factor correction and a trailing edge, pulse width modulator (PWM). The device is available in two versions; the ML4827-1 (Duty CycleMAX = 50%) and the ML4827-2 (Duty CycleMAX = 74%). The higher maximum duty cycle of the -2 allows enhanced utilization of a given transformer core's power handling capacity. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, and includes a duty cycle limit to prevent transformer saturation.
FEATURES
s s s s s
Pin-compatible with industry-standard ML4824-1 TriFault DetectTM to conform to UL1950TM requirements Available in 50% or 74% max duty cycle versions Low total harmonic distortion Reduces ripple current in the storage capacitor between the PFC and PWM sections Average current, continuous boost leading edge PFC High efficiency trailing-edge PWM can be configured for current mode or voltage mode operation Average line voltage compensation with brown-out control PFC overvoltage comparator eliminates output "runaway" due to load removal Current fed gain modulator for improved noise immunity Overvoltage protection, UVLO, and soft start
s s
s
s
s s
BLOCK DIAGRAM
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 RAMP 2 8 8V VDC 6 VCC SS 5 DC ILIMIT 9 8V 50A 1.25V
- + - +
* Some Packages Are End Of Life
1 IEAO IEA
+ -
POWER FACTOR CORRECTOR BROKEN WIRE COMPARATOR 2.7V OVP
+ -
2A VREF VCCZ 13.5V
VCC
13 VREF
VEA -
+
3.5k
+
7.5V REFERENCE
14
0.5V
+
-
S -1V
+ - -
Q Q PFC OUT Q Q 12
GAIN MODULATOR 3.5k
R S R
PFC ILIMIT
OSCILLATOR DUTY CYCLE LIMIT
S VFB 2.5V
- +
Q Q
VIN OK 1V
- +
PWM OUT 11
R DC ILIMIT VCCZ UVLO
GND 10
PULSE WIDTH MODULATOR
1
ML4827
PIN CONFIGURATION
ML4827 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W)
IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VEAO VFB VREF VCC PFC OUT PWM OUT GND DC ILIMIT
TOP VIEW
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2 3 4 5 6 7 8
IEAO IAC I SENSE V RMS SS VDC RAMP 1 RAMP 2
PFC transconductance current error amplifier output PFC gain control reference input
9 10 11
DC ILIMIT GND
PWM current limit comparator input Ground
PWM OUT PWM driver output PFC OUT VCC V REF V FB PFC driver output Positive supply (connected to an internal shunt regulator) Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input, and TriFault Detect input PFC transconductance voltage error amplifier output
Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input PFC (master) oscillator input; fOSC set by RTCT When in current mode, this pin functions as as the current sense input; when in voltage mode, it is the PWM (slave) oscillator input.
12 13 14 15
16
VEAO
2
ML4827
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Shunt Regulator Current .................................. 55mA ISENSE Voltage ..................................................-3V to 5V Voltage on Any Other Pin ... GND - 0.3V to VCCZ + 0.3V I REF ............................................................................................ 20mA IAC Input Current .................................................... 10mA Peak PFC OUT Current, Source or Sink ................ 500mA Peak PWM OUT Current, Source or Sink .............. 500mA PFC OUT, PWM OUT Energy Per Cycle .................. 1.5J Junction Temperature .............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (JA) Plastic DIP ....................................................... 80C/W Plastic SOIC .................................................. 105C/W
OPERATING CONDITIONS
Temperature Range ML4827CX ................................................. 0C to 70C ML4827IX .............................................. -40C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, ICC = 25mA, RT = 21.8k, CT = 1000pF, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP COMPARATOR Threshold Voltage Hysteresis 2.6 80 2.7 115 2.8 150 V mV VCCZ - 3V < VCC < VCCZ - 0.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 60 60 6.0 VNON INV = VINV, VEAO = 3.75V -1.5 130 2 195 10 -0.5 6.7 0.6 -90 90 75 75 1.0 2 310 17 -1.0 V VCCZ - 3V < VCC < VCCZ - 0.5V VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V -40 40 60 60 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V 0 50 2.48 85 2.55 -1 6.7 0.6 -80 80 75 75 1.0 7 120 2.62 -2 V
V A V V A A dB dB
mV A V V A A dB dB

3
ML4827
ELECTRICAL CHARACTERISTICS
SYMBOL TRI-FAULT DETECT Fault Detect HIGH Time to Fault Detect HIGH
VFB = VFAULT DETECT LOW to VFB =OPEN
(Continued)
CONDITIONS MIN TYP MAX UNITS
PARAMETER
2.6
2.7
2.8
V
1nF from VFB to GND Fault Detect LOW PFC ILIMIT COMPARATOR Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output DC ILIMIT COMPARATOR Threshold Voltage Input Bias Current Delay to Output VIN OK COMPARATOR Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100A, VRMS = VFB = 0V IAC = 50A, VRMS = 1.2V, VFB = 0V IAC = 50A, VRMS = 1.8V, VFB = 0V IAC = 100A, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Dead Time CT Discharge Current PFC Only VRAMP 2 = 0V, VRAMP 1 = 2.5V 450 4.5 Line, Temp 72 TA = 25C VCCZ - 3V < VCC < VCCZ - 0.5V 75 IAC = 100A IAC = 250A, VRMS = 1.15V, VFB = 0V 0.74 0.36 1.20 0.55 0.14 2.45 0.8 0.9 -0.8 100 0.4
1 0.5
2 0.6
ms V
-1.0 190 150
-1.15
V mV
300
ns
1.0 0.3 150
1.1 1 300
V A ns
2.55 1.0
2.65 1.2
V V
0.55 1.80 0.80 0.20 10 0.82
0.66 2.24 1.01 0.26 MHz 0.90 V
80 1 2
85
kHz % %
88 2.5 600 7.5 750 9.5
kHz V ns mA
4
ML4827
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time PWM Duty Cycle Range ML4827-1 ML4827-2 Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = 10mA, VCC = 8V Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time SUPPLY Shunt Regulator Voltage (VCCZ) VCCZ Load Regulation VCCZ Total Variation Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TA = 25C, I(VREF) = 1mA VCCZ - 3V < VCC < VCCZ - 0.5V 1mA < I(VREF) < 20mA
7.4
7.5 2 2 0.4
7.6 10 15
V mV mV %
Line, Load, Temp TJ = 125C, 1000 Hours
7.35 5
7.65 25
V mV
0 90 95 0.4 0.8 0.7 10 9.5 10.5 10 50 0.8 2.0 1.5
% % V V V V V ns
CL = 1000pF
0-44 0-64
0-47 0-70 0.4 0.8 0.7
0-50 0-74 0.8 2.0 1.5
% % V V V V V ns
10 9.5
10.5 10 50
CL = 1000pF
12.8 25mA < ICC < 55mA Load, Temp VCC = 11.8V, CL = 0 VCC < VCCZ - 0.5V, CL = 0 12 2.7 12.4
13.5 100
14.2 300 14.6
V mV V mA mA V V
0.7 16 13 3.0
1.0 19 14 3.3
5
ML4827
TYPICAL PERFORMANCE CHARACTERISTICS
250 250
TRANSCONDUCTANCE ( )
TRANSCONDUCTANCE ( )
200
200
Voltage Error Amplifier (VEA) Transconductance (gm)
400
VARIABLE GAIN BLOCK CONSTANT - K
150 100 50 0 0 1 2 VFB (V) 3 4 5 300 200 100 0 0 1 2 3 VRMS (mV) 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 OSCILLATOR GAIN MODULATOR 3.5k VEA -
+ - + -
150
100
50
0 -500
0 IEA INPUT VOLTAGE (mV)
500
Current Error Amplifier (IEA) Transconductance (gm)
4
5
Gain Modulator Transfer Characteristic (K)
1 IEAO IEA
+
POWER FACTOR CORRECTOR BROKEN WIRE COMPARATOR 2.7V
+ -
2A VREF OVP VCCZ 13.5V
VCC
13 VREF
3.5k
+
7.5V REFERENCE
14
1V
-
S -1V
+ -
Q Q PFC OUT Q Q 12
R S R
PFC ILIMIT
Figure 1. PFC Section Block Diagram.
6
ML4827
FUNCTIONAL DESCRIPTION
The ML4827 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM's line regulation. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of both the ML4827-1 and the ML4827-2 run at the same frequency as the PFC. A number of protection features have been built into the ML4827 to insure the final power supply will be as reliable as possible. These include TriFault Detect, softstart, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. TRI-FAULT DETECT PROTECTION Many power supplies manufactured for sale in the US must meet Underwriter's Laboratories (UL) standards. UL's specification UL1950 requires that no unsafe condition may result from the failure of any single circuit component. Typical system designs include external active and passive circuitry to meet this requirement. TriFault Detect is an on-chip feature of the ML4827 that monitors the VFB pin for overvoltage, undervoltage, or floating conditions which indicate that a component of the feedback path may have failed. In such an event, the PFC supply output will be disabled. These integrated redundant protections assure system compliance with UL1950 requirements. POWER FACTOR CORRECTION Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peakcharging effect which occurs on the input filter capacitor in these supplies causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4827 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line agrees with the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level) from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4827 PFC is of the current-averaging type, no slope compensation is required. PFC SECTION Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4827. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain
7
ML4827
FUNCTIONAL DESCRIPTION (Continued)
modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is termed K, and is illustrated in the Typical Performance Characteristics. 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is:
IGAINMOD = I AC VEAO VRMS 2 1V
PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 GAIN MODULATOR VEA -
+ + - - +
VREF
16 IEAO
1
IEA
Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers
(1)
More exactly, the output current of the gain modulator is given by:
. IGAINMOD = K ( VEAO - 15V) IAC
arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.7V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 125mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.58V. The VFB should be set at a level where the active and passive external power components and the ML4827 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop.
where K is in units of V-1. Note that the output current of the gain modulator is limited to 200A. Current Error Amplifier The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE VSENSE/3.5k). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the
8
ML4827
FUNCTIONAL DESCRIPTION (Continued)
Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4827's voltage error amplifier has a specially shaped nonlinearity such that under steadystate operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. Oscillator (RAMP 1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock:
fOSC = 1 t RAMP + t DEADTIME
(2)
The deadtime of the oscillator is derived from the following equation:
t RAMP = C T R T In
at VREF = 7.5V:
FG V HV
REF
REF
. - 125 . - 375
IJ K
(3)
t RAMP = C T R T 0.51
The deadtime of the oscillator may be determined using:
t DEADTIME = 25V . C T = 490 C T . mA 51
(4)
The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by:
fOSC = 1 t RAMP
(5)
EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at:
fOSC = 100kHz = 1 t RAMP
t RAMP = C T R T 0.51 = 1 10 -5
Solving for RT x CT yields 2 x 10-4. Selecting standard components values, CT = 470pF, and RT = 41.2k. The deadtime of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator deadtime, the Maximum PWM Duty Cycle is typically 45% for the ML4827-1. In many applications of the ML4827-1, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 470pF capacitor for CT.
9
ML4827
FUNCTIONAL DESCRIPTION
PWM SECTION Pulse Width Modulator The PWM section of the ML4827 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter's output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltagemode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4827, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM's RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. Maximum Duty Cycle In the ML4827-1, the maximum duty cycle of the PWM section is limited to 50% for ease of use and design. In the case of the ML4827-2, the maximum duty cycle of the PWM section is extended to 70% (typical) for enhanced utilization of the inductor. Operation at 70% duty cycle requires special care in circuit design to avoid volt-second imbalances, and/or high-voltage damage to the PWM switch transistor(s). Using the ML4827-2 The ML4827-2's higher PWM duty cycle offers several design advantages that skilled power supply and magnetics engineers can take advantage of, including: * * * Reduced RMS and peak PWM switch currents Reduced RMS and peak PWM transformer currents Easier RFI/EMI filtering due to lower peak currents (Continued) fewer turns on forward converter reset windings. Long duty cycles, by allowing greater utilization of the PFC's stored charge, can also lower the cost of PFC bus capacitors while still offering long "hold-up" times. NOTE: during the time when the PWM switch is off (the reset or flyback periods), increasing duty cycles will result in rapidly increasing peak voltages across the switch. This result of high PWM duty cycles requires greater care be used in circuit design. Relevant design issues include: * * * Higher voltage (>1000V) PWM switches More carefully designed and tested PWM transformers Clamps and/or snubbers when needed
Also, slope compensation will be required in most current mode PWM designs. For those who want to approach the limits of attainable performance (most commonly high-volume, low-cost supplies), the ML4827-2's 70% maximum PWM duty cycle offers several desirable design capabilities. Using a 70% duty cycle makes it essential to perform a careful magnetics design and component stress analysis before finalizing designs with the ML4827-2. THE ML4827-2: SPECIAL CONSIDERATIONS FOR HIGH DUTY CYCLES The use of the ML4827-1, especially with the type of PWM output stage shown in the Application Circuit of Figure 6, is straightforward due to the limitation of the PWM duty cyle to 50% maximum. In fact, one of the advantages of the "two-transistor single-ended forward converter" shown in Figure 6 is that it will necessarily reset the core, with no additional winding required, as long as the core does not go into saturation during the topology's maximum permissible 50% duty cycle. For the "-2" version of the ML4827, the maximum duty cycle () of the PWM is nominally 70%. As the twotransistor single-ended forward converter cannot be used at duty cycles greater than 50%, high- applications require the use of either a single-transistor forward converter (with a transformer reset winding), or a flyback output stage. In either case, special concerns arise regarding the peak voltage appearing on the PWM switch transistor, the PWM output transformer, and associated power components as the duty cycle increases. For any output stage topology, the available on-time (core "set" time) is (1/fPWM) x , while the reset time for the core of the PWM output transformer is (1/fPWM) x (1-). This means that the magnetizing inductance of the core charges for a period of (1/fPWM) x , and must be completely discharged during a period of (1/fPWM) x (1-). The ratio of these two periods, multiplied by the maximum value of the PFC's VBUSS, yields the minimum
These reduced currents can result in cost savings by allowing smaller PWM transformer primary windings and
10
ML4827
FUNCTIONAL DESCRIPTION
(Continued) at the lowest guaranteed value for , to ensure that the magnetics will deliver full output power with any individual ML4827. In actual operation, the choice of MIN = 60% will allow some tolerance for the timing capacitors and resistors. A tolerance on (RRAMP2 x CRAMP2) of 2% is the simplest "brute force" way to achieve the desired result. This should be combined with an external duty cycle clamp. This protects the PWM circuitry against the condition in which the output has been shorted, and the error amplifier output (VDC) would otherwise be driven to its upper rail. One method which works well when the PWM is used in voltage mode is to limit the maximum input to the PWM feedback voltage (VDC). If the voltage available to this pin is derived from the ML4827's 7.5V VREF, it will be in close ratio to the charging time of the RAMP2 capacitor. This will be true whether the RAMP2 capacitor is charged from VREF, or, as is more commonly done in voltage-mode applications, from the output of the PFC Stage (the "feedforward" configuration). Figure 3 shows such a duty cycle clamp. If the ML4827-2's PWM is to be used in a current-mode design, the PWM stage will require slope compensation. This can be done by any of the standard industry techniques. Note that the ramp to use for this slope compensation is the voltage on RAMP1. voltage for which the PWM output transistor must be rated. Frequently, the design of the tranformer's reset winding, and/or of the output transistor's snubbers or clamps, require an additional voltage margin of 100V to 200V. To put some numbers into the discussion, with a given VBUSS(MAX) of 400V: 1. For = 50%: VRESET = {[(1/fPWM) x ]/[(1/fPWM) x (1-)]} x 400V = 0.50/0.50 x 400V = 400V 2. For = 55%: VRESET = 0.55/0.45 x 400V = 489V 3. For = 60%: VRESET = 0.60/0.40 x 400V = 600V 4. For = 64% (Data Sheet Lower Limit Value): VRESET = 0.64/0.36 x 400V = 711V 5. For = 70%: VRESET = 0.70/0.30 x 400V = 933V 6. For = 74% (Data Sheet Upper Limit Value): VRESET = 0.74/0.26 x 400V = 1138V It is economically desirable to design for the lowest meaningful voltage on the output MOSFET. It is simultaneously necessary to design the circuit to operate
PFC VBUSS RFB1 RRAMP2 VFB RFB2
RAMP2 CRAMP2
VREF R1
PWM ERROR AMP
VDC R2
MAX =
R2 VREF R1 + R2
VRAMP2 (PEAK)
Figure 3. ML4827- PWM Duty Cycle Clamp for Voltage-Made Operation
11
ML4827
FUNCTIONAL DESCRIPTION
(Continued) It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS:
C SS = 5ms x 50A 220nF 125V .
Using the recommended values of MIN = 60% and MAX = 64% for a high- application, a MOSFET switch with a Drain-Source breakdown voltage of 900V, or in some cases as low as 800V, can reliably be used. Such parts are readily and inexpensively available from a number of vendors. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM's output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), which will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 50A supplies the charging current for the capacitor, and startup of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation:
C SS = t DELAY 50A 125V .
Generating VCC The ML4827 is a current-fed part. It has an internal shunt voltage regulator, which is designed to regulate the voltage internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs. It is important to limit the current through the part to avoid overheating or destroying it. This can be easily done with a single resistor in series with the VCC pin, returned to a bias supply of typically 18V to 20V. The resistor's value must be chosen to meet the operating current requirement of the ML4827 itself (19mA max) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC limit of 14.6V (max) and the ML4827 driving a total gate charge of 110nC at 100kHz (e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is:
IGATEDRIVE = 100kHz 100nC = 11 mA RBIAS = 20V - 14.6V = 180 mA 19mA + 11
(7) (8)
(6)
To check the maximum dissipation in the ML4827, find the current at the minimum VCC (12.4V):
ICC = 20V - 12.4V = 42.2mA 180
where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay.
(9)
The maximum allowable ICC is 55mA, so this is an acceptable design.
VBIAS
RBIAS
VCC ML4827 GND 10nF CERAMIC 1F CERAMIC
Figure 4. External Component Connections to VCC
12
ML4827
FUNCTIONAL DESCRIPTION
(Continued) trailing edge modulation is determined during the ON time of the switch. Figure 5 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 6 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With The ML4827 should be locally bypassed with a 10nF and a 1F ceramic capacitor. In most applications, an electrolytic capacitor of between 100F and 330F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the
L1 + I1 VIN
SW2
I2
I3 I4
DC
SW1
C1
RL
RAMP
VEAO REF U3 + -EA DFF RAMP OSC U4 CLK + - U1 R Q D U2 Q CLK VSW1 TIME
TIME
Figure 5. Typical Trailing Edge Control Scheme.
L1 + I1 VIN
SW2
I2
I3 I4
DC
SW1
C1
RL
RAMP
VEAO
REF
U3 + -EA
TIME VEAO + - CMP U1 DFF R Q D U2 Q CLK VSW1
RAMP OSC U4 CLK
TIME
Figure 6. Typical Leading Edge Control Scheme.
13
ML4827
LEADING/TRAILING MOD.
(Continued)
TYPICAL APPLICATIONS
Figure 7 is the application circuit for a complete 100W power factor corrected power supply. This circuit was designed using the methods and topology detailed in Application Note 33.
such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method.
AC INPUT 85 TO 265VAC
C1 470nF
F1 3.15A L1 3.1mH Q1 IRF840 R2A 357k R1A 499k R27 39k 2W R21 22 D1 8A, 600V, "FRED" Diode Q2 R17 IRF830 33 C25 100nF T1 R30 4.7k R15 3 D6 BYV26C D5 BYV26C D7 15V T2 L2 D11 MBR2545CT 33H C24 1F 12VDC
C4 10nF
C5 100F
BR1 4A, 600V
R2B 357k
R28 180 C3 470nF R1B 499k R3 75k C7 220pF R12 27k C6 1nF
D3 BYV26C
C20 1F
C21 1800F
RTN R24 1.2k
C30 330F
C12 10F R7A 178k
R14 33
Q3 IRF830
10k R23 1.5k
C22 4.7F R18 220 9W R22 8.66k
D12 1N5401 D13 1N5401
R19 220 R7B 178k
R20 1.1 MOC 8102
R26 10k
C23 100nF R25 2.26k
C2 470nF
R4 13k
TL431
1 2 3
R5 300m 1W
IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2
VEAO VFB VREF VCC PFC OUT PWM OUT GND DC ILIMIT
16 15 14 13 12 11 10 9
D8 1N5818 C15 10nF C16 1F C13 100nF C14 1F R8 2.37k C31 1nF R11 750k C8 82nF C9 8.2nF
4 5
C19 1F
6 7 8
D10 1N5818 L1: L2: T1: T2: Premier Magnetics #TSD-734 33H, 10A DC Premier Magnetics #TSD-736 Premier Magnetics #TSD-735
ML4827-1
C18 470pF
R6 41.2k
R10 6.2k
C17 220pF
Premier Magnetics: (714) 362-4211
C11 10nF
Figure 7. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.
14
ML4827
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P16 16-Pin PDIP
0.740 - 0.760 (18.79 - 19.31) 16
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.02 MIN (0.50 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S16N 16-Pin Narrow SOIC
0.386 - 0.396 (9.80 - 10.06) 16
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
15
ML4827
ORDERING INFORMATION
PART NUMBER ML4827CP-1 ML4827CP-2 ML4827CS-1 ML4827CS-2 ML4827IP-1 ML4827IP-2 ML4827IS-1 ML4827IS-2 MAX DUTY CYCLE 50% 74% 50% 74% 50% 74% 50% 74% TEMPERATURE RANGE 0C 0C 0C 0C to 70C to 70C to 70C to 70C to to to to 85C 85C 85C 85C PACKAGE 16-Pin PDIP (P16) 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin Narrow SOIC (S16N) 16-Pin PDIP (P16) (EOL) 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) (EOL) 16-Pin Narrow SOIC (S16N)
-40C -40C -40C -40C
(c) Micro Linear 1998.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
DS4827-01
16

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